This invention relates in general to the field of electronic systems, and more particularly, to an improved system and method for controlling leakage current in an integrated electronic device using current limiting devices.
Integrated circuit devices must be designed so that they provide enough current to accomplish the tasks logically assigned to them and they must accomplish these tasks without drawing an inordinate amount of power. There is a direct design tradeoff between drive current and leakage current in the design of an electronic system. A device such as a transistor that is designed to provide a fast switching operation and designed to provide a large amount of current will also unfortunately result in an unacceptable amount of leakage current when the device is turned off. This leakage current can negatively affect the power consumption of the entire device.
To address the leakage current, prior techniques have used series resistors and current limiting devices in the current path of such transistors. The problem is that these devices and other techniques are not always necessary. Transistors that have excessively high leakage current do not consistently appear. The characteristics of these transistors are dependent upon process variations and sometimes the operating environments in which the transistors are placed. In cases where the transistors do not have an excessively large leakage currents or for applications where such leakage current is not of primary concern, the presence of the current limiting devices unnecessarily impedes the speed and operational capabilities in the integrated system.
Accordingly, a need has arisen for a system and method of addressing leakage current within integrated devices that is applicable where needed but does not impede the operation of devices that do not demonstrate unacceptable leakage current.
According to the teachings of the present invention, a system and method for controlling leakage current are provided that substantially eliminate or reduce problems associated with prior techniques and systems. According to one embodiment of the present invention, a method for controlling leakage current in an integrated circuit is provided that determines whether a current carrying device within the integrated circuit demonstrates an unacceptable level of leakage current. Responsive to that determination, a control node within the circuit is then selectively connected to a supply voltage such as ground potential or VDD to adjust the effective threshold voltage of the subject device.
According to one specific embodiment of the present invention, a source resistance transistor in series with a current carrying device has its control gate coupled to either ground potential or the supply voltage depending upon the inherent threshold voltage or leakage of the current carrying device. If the source resistance transistor is turned to its high conduction state, the threshold voltage of the current carrying device is effectively unchanged. If the source resistance transistor is put in a low conduction state, the effective threshold voltage of the current carrying device will be changed to a level which will reduce the amount of leakage current through the current carrying device.
According to an alternate embodiment of the present invention, a back-gate contact to a current carrying device is available for selective connection to a supply voltage such as ground potential or VDD. The back-gate contact may comprise for example, a contact to a buried gate, a well contact or a substrate bias contact. According to the inherent characteristics of the device and the application, the back-gate contact can be coupled to a supply voltage that will relatively increase or decrease the threshold voltage of the current carrying device.